• Andi Kleen's avatar
    perf/x86/intel: Streamline LBR MSR handling in PMI · 1a78d937
    Andi Kleen authored
    The perf PMI currently does unnecessary MSR accesses when
    LBRs are enabled. We use LBR freezing, or when in callstack
    mode force the LBRs to only filter on ring 3.
    
    So there is no need to disable the LBRs explicitely in the
    PMI handler.
    
    Also we always unnecessarily rewrite LBR_SELECT in the LBR
    handler, even though it can never change.
    
     5)               |  /* write_msr: MSR_LBR_SELECT(1c8), value 0 */
     5)               |  /* read_msr: MSR_IA32_DEBUGCTLMSR(1d9), value 1801 */
     5)               |  /* write_msr: MSR_IA32_DEBUGCTLMSR(1d9), value 1801 */
     5)               |  /* write_msr: MSR_CORE_PERF_GLOBAL_CTRL(38f), value 70000000f */
     5)               |  /* write_msr: MSR_CORE_PERF_GLOBAL_CTRL(38f), value 0 */
     5)               |  /* write_msr: MSR_LBR_SELECT(1c8), value 0 */
     5)               |  /* read_msr: MSR_IA32_DEBUGCTLMSR(1d9), value 1801 */
     5)               |  /* write_msr: MSR_IA32_DEBUGCTLMSR(1d9), value 1801 */
    
    This patch:
    
      - Avoids disabling already frozen LBRs unnecessarily in the PMI
      - Avoids changing LBR_SELECT in the PMI
    Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
    Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
    Cc: eranian@google.com
    Link: http://lkml.kernel.org/r/1426871484-21285-1-git-send-email-andi@firstfloor.orgSigned-off-by: default avatarIngo Molnar <mingo@kernel.org>
    1a78d937
perf_event_intel_lbr.c 23.8 KB