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Richard Leitner authored
Some PHYs (for example the SMSC LAN8710/LAN8720) doesn't allow turning the refclk on and off again during operation (according to their datasheet). Nonetheless exactly this behaviour was introduced for power saving reasons by commit e8fcfcd5 ("net: fec: optimize the clock management to save power"). Therefore add support for the phy_reset_after_clk_enable function from phylib to mitigate this issue. Generally speaking this issue is only relevant if the ref clk for the PHY is generated by the SoC and therefore the PHY is configured to "REF_CLK In Mode". In our specific case (PCB) this problem does occur at about every 10th to 50th POR of an LAN8710 connected to an i.MX6SOLO SoC. The typical symptom of this problem is a "swinging" ethernet link. Similar issues were reported by users of the NXP forum: https://community.nxp.com/thread/389902 https://community.nxp.com/message/309354 With this patch applied the issue didn't occur for at least a few hundret PORs of our board. Fixes: e8fcfcd5 ("net: fec: optimize the clock management to save power") Signed-off-by:
Richard Leitner <richard.leitner@skidata.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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