• Vineet Gupta's avatar
    ARCv2: Support for ARCv2 ISA and HS38x cores · 1f6ccfff
    Vineet Gupta authored
    The notable features are:
        - SMP configurations of upto 4 cores with coherency
        - Optional L2 Cache and IO-Coherency
        - Revised Interrupt Architecture (multiple priorites, reg banks,
            auto stack switch, auto regfile save/restore)
        - MMUv4 (PIPT dcache, Huge Pages)
        - Instructions for
    	* 64bit load/store: LDD, STD
    	* Hardware assisted divide/remainder: DIV, REM
    	* Function prologue/epilogue: ENTER_S, LEAVE_S
    	* IRQ enable/disable: CLRI, SETI
    	* pop count: FFS, FLS
    	* SETcc, BMSKN, XBFU...
    Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
    1f6ccfff
entry.h 6.72 KB