• Afzal Mohammed's avatar
    bus: omap_l3_noc: ignore masked out unclearable targets · 2100b595
    Afzal Mohammed authored
    Errors that cannot be cleared (determined by reading REGERR register)
    are currently handled by masking it. Documentation states that REGERR
    "Checks which application/debug error sources are active" - it does not
    indicate that this is "interrupt status" - masked out status represented
    eventually in the irq line to MPU.
    For example:
    
    Lets say module 0 bit 8(0x100) was unclearable, we do the mask it from
    generating further errors. However in the following cases:
    a) bit 9 of Module 0
    OR
    b) any bit of Module 1+
    occur, the interrupt handler wrongly assumes that the raw interrupt
    status of module 0 bit 8 is the root cause of the interrupt, and
    returns. This causes unhandled interrupt and resultant infinite
    interrupts.
    
    Fix this scenario by storing the events we masked out and masking raw
    status with masked ones before identifying and handling the error.
    Reported-by: default avatarVaibhav Hiremath <hvaibhav@ti.com>
    Signed-off-by: default avatarAfzal Mohammed <afzal@ti.com>
    Tested-by: default avatarVaibhav Hiremath <hvaibhav@gmail.com>
    Signed-off-by: default avatarSekhar Nori <nsekhar@ti.com>
    Signed-off-by: default avatarNishanth Menon <nm@ti.com>
    Tested-by: default avatarSekhar Nori <nsekhar@ti.com>
    2100b595
omap_l3_noc.c 7.99 KB