• James Hogan's avatar
    clk: clk-divider: fix divisor > 255 bug · 778037e1
    James Hogan authored
    Commit 6d9252bd (clk: Add support for power of two type dividers)
    merged in v3.6 added the _get_val function to convert a divisor value to
    a register field value depending on the flags. However it used the type
    u8 for the div field, causing divisors larger than 255 to be masked
    and the resultant clock rate to be too high.
    
    E.g. in my case an 11bit divider was supposed to divide 24.576 MHz down
    to 32.768KHz. The divisor was correctly calculated as 750 (0x2ee). This
    was masked to 238 (0xee) resulting in a frequency of 103.26KHz.
    Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
    Cc: Rajendra Nayak <rnayak@ti.com>
    Cc: linux-arm-kernel@lists.infradead.org
    Cc: stable@vger.kernel.org
    Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
    778037e1
clk-divider.c 9.11 KB