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Stefan Agner authored
The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT and NAND_CLK_ROOT. However, the gate has been in the chain of the latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT only, e.g. as required by APBH-Bridge-DMA. Add new clocks which represent the clock after the gate, and use a shared clock gate to correctly model the hardware. Signed-off-by:
Stefan Agner <stefan@agner.ch> Tested-by:
Fabio Estevam <fabio.estevam@nxp.com> Acked-by:
Han Xu <han.xu@nxp.com> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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