• Wolfram Sang's avatar
    ASoC: sgtl5000: fix cache handling · 151798f8
    Wolfram Sang authored
    Cache handling in this driver is broken. The chip has 16-bit registers, yet the
    register numbers also increase by 2 per register, i.e.  there are only
    even-numbered registers. The cache in this driver, though, simply increments
    register numbers, so it does need some mapping as seen in
    sgtl5000_restore_regs(), note the '>> 1':
    
    	snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL,
                            cache[SGTL5000_CHIP_LINREG_CTRL >> 1]);
    
    That, of course, won't work with snd_soc_update_bits(). (Thus, we won't even
    notice the missing register 0x1c in the default regs which shifted all follwing
    registers to wrong values.) Noticed on the MX28EVK where enabling the regulators
    simply locked up the chip.
    
    Refactor the routines and use a properly sized default_regs array which matches
    the register layout of the underlying chip, i.e. create a truly flat cache.
    This also saves some code which should make up for the bigger array a little.
    When soc-core will somewhen have another cache type which handles a step size,
    this conversion will also ease the transition.
    Signed-off-by: default avatarWolfram Sang <w.sang@pengutronix.de>
    Tested-by: default avatarDong Aisheng <b29396@freescale.com>
    Tested-by: default avatarShawn Guo <shawn.guo@linaro.org>
    Acked-by: default avatarLiam Girdwood <lrg@ti.com>
    Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
    Cc: stable@kernel.org
    151798f8
sgtl5000.c 36.4 KB