• Will Deacon's avatar
    ARM: 6943/1: mm: use TTBR1 instead of reserved context ID · 52af9c6c
    Will Deacon authored
    On ARMv7 CPUs that cache first level page table entries (like the
    Cortex-A15), using a reserved ASID while changing the TTBR or flushing
    the TLB is unsafe.
    
    This is because the CPU may cache the first level entry as the result of
    a speculative memory access while the reserved ASID is assigned. After
    the process owning the page tables dies, the memory will be reallocated
    and may be written with junk values which can be interpreted as global,
    valid PTEs by the processor. This will result in the TLB being populated
    with bogus global entries.
    
    This patch avoids the use of a reserved context ID in the v7 switch_mm
    and ASID rollover code by temporarily using the swapper_pg_dir pointed
    at by TTBR1, which contains only global entries that are not tagged
    with ASIDs.
    Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
    Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
    Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
    52af9c6c
proc-v7.S 13.2 KB