The DI clock selection was very rudimentary: it would statically use
either the IPU internal clock or the DI external clock depending on
which "encoder" was being used.  In the case of HDMI, it would always
use the IPU clock.

Moreover, using the IPU clock resulted in fractional divisors, which
are achieved by skipping clock pulses.  This can result in the HDMI
PHY PLL being frequency modulated, and the attached device is then
unable to properly lock on to the TMDS clock.

We need at least 1% accurate and stable clocks for HDMI.

Arrange for the DI clock to be sourced from the IPU internal clock
if it can satisfy our requirements, otherwise switch to the DI
external clock and try and set the external clock to our desired
pixel clock rate.
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>