Add devicetree YAML binding for Cortex A7 PLL clock in Qualcomm
platforms like SDX55.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20210118041156.50016-4-manivannan.sadhasivam@linaro.orgReviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>