• Raviteja Narayanam's avatar
    Revert "i2c: cadence: Fix the hold bit setting" · 2bf308bb
    Raviteja Narayanam authored
    [ Upstream commit 0db9254d ]
    
    This reverts commit d358def7.
    
    There are two issues with "i2c: cadence: Fix the hold bit setting" commit.
    
    1. In case of combined message request from user space, when the HOLD
    bit is cleared in cdns_i2c_mrecv function, a STOP condition is sent
    on the bus even before the last message is started. This is because when
    the HOLD bit is cleared, the FIFOS are empty and there is no pending
    transfer. The STOP condition should occur only after the last message
    is completed.
    
    2. The code added by the commit is redundant. Driver is handling the
    setting/clearing of HOLD bit in right way before the commit.
    
    The setting of HOLD bit based on 'bus_hold_flag' is taken care in
    cdns_i2c_master_xfer function even before cdns_i2c_msend/cdns_i2c_recv
    functions.
    
    The clearing of HOLD bit is taken care at the end of cdns_i2c_msend and
    cdns_i2c_recv functions based on bus_hold_flag and byte count.
    Since clearing of HOLD bit is done after the slave address is written to
    the register (writing to address register triggers the message transfer),
    it is ensured that STOP condition occurs at the right time after
    completion of the pending transfer (last message).
    Signed-off-by: default avatarRaviteja Narayanam <raviteja.narayanam@xilinx.com>
    Acked-by: default avatarMichal Simek <michal.simek@xilinx.com>
    Signed-off-by: default avatarWolfram Sang <wsa@kernel.org>
    Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
    2bf308bb
i2c-cadence.c 29 KB