• Andrew Morton's avatar
    [PATCH] ppc64: strengthen I/O and memory barriers · 2c3956c9
    Andrew Morton authored
    From: Paul Mackerras <paulus@samba.org>
    
    After I sent the recent patch to include/asm-ppc64/io.h which put stronger
    barriers in the I/O accessor macros, Paul McKenney pointed out to me that a
    writex/outx could still slide out from inside a spinlocked region.  This patch
    makes the barriers a bit stronger so that this can't happen.  It means that we
    need to use a sync instruction for wmb (a full "heavyweight" sync), since
    drivers rely on wmb for ordering between writes to system memory and writes to
    a device.
    
    I have left smb_wmb() as a lighter-weight barrier that orders stores, and
    doesn't impose an ordering between cacheable and non-cacheable accesses (the
    amusingly-named eieio instruction).  I am assuming here that smp_wmb is only
    used for ordering stores to system memory so that another cpu will see them in
    order.  It can't be used for enforcing any ordering that a device will see,
    because it is just a gcc barrier on UP.
    
    This also changes the spinlock/rwlock unlock code to use lwsync ("light-weight
    sync") rather than eieio, since eieio doesn't order loads, and we need to
    ensure that loads stay inside the spinlocked region.
    2c3956c9
io.h 13 KB