• Huacai Chen's avatar
    MIPS: Flush wrong invalid FTLB entry for huge page · 2d1af1b7
    Huacai Chen authored
    commit 0115f6cb upstream.
    
    On VTLB+FTLB platforms (such as Loongson-3A R2), FTLB's pagesize is
    usually configured the same as PAGE_SIZE. In such a case, Huge page
    entry is not suitable to write in FTLB.
    
    Unfortunately, when a huge page is created, its page table entries
    haven't created immediately. Then the TLB refill handler will fetch an
    invalid page table entry which has no "HUGE" bit, and this entry may be
    written to FTLB. Since it is invalid, TLB load/store handler will then
    use tlbwi to write the valid entry at the same place. However, the
    valid entry is a huge page entry which isn't suitable for FTLB.
    
    Our solution is to modify build_huge_handler_tail. Flush the invalid
    old entry (whether it is in FTLB or VTLB, this is in order to reduce
    branches) and use tlbwr to write the valid new entry.
    Signed-off-by: default avatarRui Wang <wangr@lemote.com>
    Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
    Cc: John Crispin <john@phrozen.org>
    Cc: Steven J . Hill <Steven.Hill@caviumnetworks.com>
    Cc: Fuxin Zhang <zhangfx@lemote.com>
    Cc: Zhangjin Wu <wuzhangjin@gmail.com>
    Cc: Huacai Chen <chenhc@lemote.com>
    Cc: linux-mips@linux-mips.org
    Patchwork: https://patchwork.linux-mips.org/patch/15754/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
    Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
    2d1af1b7
tlbex.c 65.9 KB