• Jacob Pan's avatar
    x86, apbt: Moorestown APB system timer driver · bb24c471
    Jacob Pan authored
    Moorestown platform does not have PIT or HPET platform timers.  Instead it
    has a bank of eight APB timers.  The number of available timers to the os
    is exposed via SFI mtmr tables.  All APB timer interrupts are routed via
    ioapic rtes and delivered as MSI.
    Currently, we use timer 0 and 1 for per cpu clockevent devices, timer 2
    for clocksource.
    Signed-off-by: default avatarJacob Pan <jacob.jun.pan@intel.com>
    LKML-Reference: <43F901BD926A4E43B106BF17856F0755A318D2D2@orsmsx508.amr.corp.intel.com>
    Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
    bb24c471
apb_timer.h 2.11 KB