drivers/clk/at91/clk-sam9x60-pll.c · 35d06f74785cc8d108dcb1e3324b2404fb39df0b · Kirill Smelkov / linux

clk: at91: sam9x60-pll: use frac when setting frequency · 35d06f74

Claudiu Beznea authored Jul 22, 2020

In commit a436c2a4 ("clk: at91: add sam9x60 PLL driver")
the fractional part of PLL wasn't set on registers but it was
calculated and taken into account for determining div and mul
(see sam9x60_pll_get_best_div_mul()).

Fixes: a436c2a4 ("clk: at91: add sam9x60 PLL driver")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1595403506-8209-7-git-send-email-claudiu.beznea@microchip.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>

35d06f74

clk-sam9x60-pll.c 8.25 KB

Replace clk-sam9x60-pll.c