• Paul Mackerras's avatar
    KVM: PPC: Book3S HV: Set LPCR[HDICE] before writing HDEC · 35dfb43c
    Paul Mackerras authored
    POWER8 and POWER9 machines have a hardware deviation where generation
    of a hypervisor decrementer exception is suppressed if the HDICE bit
    in the LPCR register is 0 at the time when the HDEC register
    decrements from 0 to -1.  When entering a guest, KVM first writes the
    HDEC register with the time until it wants the CPU to exit the guest,
    and then writes the LPCR with the guest value, which includes
    HDICE = 1.  If HDEC decrements from 0 to -1 during the interval
    between those two events, it is possible that we can enter the guest
    with HDEC already negative but no HDEC exception pending, meaning that
    no HDEC interrupt will occur while the CPU is in the guest, or at
    least not until HDEC wraps around.  Thus it is possible for the CPU to
    keep executing in the guest for a long time; up to about 4 seconds on
    POWER8, or about 4.46 years on POWER9 (except that the host kernel
    hard lockup detector will fire first).
    
    To fix this, we set the LPCR[HDICE] bit before writing HDEC on guest
    entry.
    Signed-off-by: default avatarPaul Mackerras <paulus@ozlabs.org>
    35dfb43c
book3s_hv_interrupts.S 3.99 KB