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Children of NAND controllers have only chip select, so address without
the size.  Correct size-cells as reported by dtbs_check:

  s5pv210-galaxys.dtb: onenand@b0600000: #size-cells:0:0: 0 was expected

Link: https://lore.kernel.org/r/20240313191148.21792-2-krzysztof.kozlowski@linaro.org

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>