• Antony Pavlov's avatar
    MIPS: ath79: update devicetree clock support for AR9132 · 3bdf1071
    Antony Pavlov authored
    Current ath79 clock.c code does not read reference clock and
    pll setup from devicetree. E.g. you can set any clock rate value
    in board DTS but it will have no effect on the real clk calculation.
    
    This patch fixes some AR9132 devicetree clock support defects:
    
      * clk initialization function ath79_clocks_init_dt_ng()
        is introduced; it actually gets pll block base register
        address and reference clock from devicetree;
      * pll register parsing code is moved to the separate
        ar724x_clk_init() function; this function
        can be called from platform code or from devicetree code.
    
    Also mips_hpt_frequency value is set from dt, so the appropriate
    clock parameter is added to the cpu@0 devicetree node.
    
    The same approach can be used for adding AR9331 devicetree support.
    Signed-off-by: default avatarAntony Pavlov <antonynpavlov@gmail.com>
    Cc: Gabor Juhos <juhosg@openwrt.org>
    Cc: Alban Bedel <albeu@free.fr>
    Cc: Michael Turquette <mturquette@baylibre.com>
    Cc: Stephen Boyd <sboyd@codeaurora.org>
    Cc: Rob Herring <robh+dt@kernel.org>
    Cc: linux-clk@vger.kernel.org
    Cc: linux-mips@linux-mips.org
    Cc: devicetree@vger.kernel.org
    Patchwork: https://patchwork.linux-mips.org/patch/12876/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
    3bdf1071
clock.c 14.3 KB