• Imre Deak's avatar
    drm/i915: sanitize rps irq enabling · 3cc134e3
    Imre Deak authored
    Atm we first enable the RPS interrupts then we clear any pending ones.
    By this we could lose an interrupt arriving after we unmasked it. This
    may not be a problem as the caller should handle such a race, but logic
    still calls for the opposite order. Also we can delay enabling the
    interrupts until after all the RPS initialization is ready with the
    following order:
    
    1. disable left-over RPS (earlier via intel_uncore_sanitize)
    2. clear any pending RPS interrupts
    3. initialize RPS
    4. enable RPS interrupts
    
    This also allows us to do the 2. and 4. step the same way for all
    platforms, so let's follow this order to simplifying things.
    
    Also make sure any queued interrupts are also cleared.
    
    v2:
    - rebase on the GEN9 patches where we don't support RPS yet, so we
      musn't enable RPS interrupts on it (Paulo)
    v3:
    - avoid enabling RPS interrupts on GEN>9 too (Paulo)
    - clarify the RPS init sequence in the log message (Chris)
    - add POSTING_READ to gen6_reset_rps_interrupts() (Paulo)
    - WARN if any PM_IIR bits are set in gen6_enable_rps_interrupts()
      (Paulo)
    Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
    Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    3cc134e3
intel_pm.c 203 KB