Tests on PLI12096bc showed that sometimes a small delay is necessary
after a write operation before a new operation can be processed.
If not respected the device will probably NACK the data phase of
the SMBus transaction. Tests showed that the probability to observe
transaction errors can be raised by either reading sensor data or
toggling the regulator enable.

Further tests showed that 250 microseconds, as used previously for
the CLEAR_FAULTS workaround, is sufficient.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Message-ID: <20240902075319.585656-5-patrick.rudolph@9elements.com>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>