• Tony Lindgren's avatar
    bus: ti-sysc: Assert reset only after disabling clocks · 4097c9a6
    Tony Lindgren authored
    The rstctrl reset must be asserted after gating the module clock as
    described in the TRM at least for IVA. Otherwise the rstctrl reset
    done with module clock enabled can hang the system.
    
    Note that this issue is has been only seen with related IVA changes
    that we do not currently have merged. So probably no need to apply
    this patch as a fix.
    Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
    4097c9a6
ti-sysc.c 76.6 KB