Don't clear ep0 status phase handshake during endpoint reset ... at least
one driver emits so much debug output before resetting endpoints that the
reset happens late enough to make the chip break protocol.

Also handle resets IRQs a bit differently:  they can happen twice during
enumeration, which can worsen the other problem.

From:          Alex Sanks <alex@netchip.com>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Greg Kroah-Hartman <greg@kroah.com>