• Paulo Zanoni's avatar
    drm/i915: implement IPS feature · 42db64ef
    Paulo Zanoni authored
    Intermediate Pixel Storage is a feature that should reduce the number
    of times the display engine wakes up memory to read pixels, so it
    should allow deeper PC states. IPS can only be enabled on ULT pipe A
    with 8:8:8 pipe pixel formats.
    
    With eDP 1920x1080 and correct watermarks but without FBC this moves
    my PC7 residency from 2.5% to around 38%.
    
    v2: - It's tied to pipe A, not port A
        - Add pipe_config support (Chris)
        - Add some assertions (Chris)
        - Rebase against latest dinq
    v3: - Don't ever set ips_enabled to false (Daniel)
        - Only check for ips_enabled at hsw_disable_ips (Daniel)
    v4: - Add hsw_compute_ips_config (Daniel)
        - Use the new dump_pipe_config (Daniel)
    Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
    Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@gmail.com>
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    42db64ef
intel_display.c 267 KB