• Andrew Jones's avatar
    RISC-V: Enable cbo.zero in usermode · 43c16d51
    Andrew Jones authored
    When Zicboz is present, enable its instruction (cbo.zero) in
    usermode by setting its respective senvcfg bit. We don't bother
    trying to set this bit per-task, which would also require an
    interface for tasks to request enabling and/or disabling. Instead,
    permanently set the bit for each hart which has the extension when
    bringing it online.
    
    This patch also introduces riscv_cpu_has_extension_[un]likely()
    functions to check a specific hart's ISA bitmap for extensions.
    Prior to checking the specific hart's bitmap in these functions
    we try the bitmap which represents the LCD of extensions, but only
    when we know it will use its optimized, alternatives path by gating
    its call on CONFIG_RISCV_ALTERNATIVE. When alternatives are used, the
    compiler ensures that the invocation of the LCD search becomes a
    constant true or false. When it's true, even the new functions will
    completely vanish from their callsites. OTOH, when the LCD check is
    false, we need to do a search of the hart's ISA bitmap. Had we also
    checked the LCD bitmap without the use of alternatives, then we would
    have ended up with two bitmap searches instead of one.
    Signed-off-by: default avatarAndrew Jones <ajones@ventanamicro.com>
    Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
    Link: https://lore.kernel.org/r/20230918131518.56803-10-ajones@ventanamicro.comSigned-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
    43c16d51
cpufeature.c 20.7 KB