• Ben Widawsky's avatar
    drm/i915: Add second slice l3 remapping · 35a85ac6
    Ben Widawsky authored
    Certain HSW SKUs have a second bank of L3. This L3 remapping has a
    separate register set, and interrupt from the first "slice". A slice is
    simply a term to define some subset of the GPU's l3 cache. This patch
    implements both the interrupt handler, and ability to communicate with
    userspace about this second slice.
    
    v2:  Remove redundant check about non-existent slice.
    Change warning about interrupts of unknown slices to WARN_ON_ONCE
    Handle the case where we get 2 slice interrupts concurrently, and switch
    the tracking of interrupts to be non-destructive (all Ville)
    Don't enable/mask the second slice parity interrupt for ivb/vlv (even
    though all docs I can find claim it's rsvd) (Ville + Bryan)
    Keep BYT excluded from L3 parity
    
    v3: Fix the slice = ffs to be decremented by one (found by Ville). When
    I initially did my testing on the series, I was using 1-based slice
    counting, so this code was correct. Not sure why my simpler tests that
    I've been running since then didn't pick it up sooner.
    Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
    Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    35a85ac6
i915_drm.h 32.1 KB