• Fenghua Yu's avatar
    x86/cpufeature: Add RDT CPUID feature bits · 4ab15864
    Fenghua Yu authored
    Check CPUID leaves for all the Resource Director Technology (RDT)
    Cache Allocation Technology (CAT) bits.
    
    Presence of allocation features:
      CPUID.(EAX=7H, ECX=0):EBX[bit 15]	X86_FEATURE_RDT_A
    
    L2 and L3 caches are each separately enabled:
      CPUID.(EAX=10H, ECX=0):EBX[bit 1]	X86_FEATURE_CAT_L3
      CPUID.(EAX=10H, ECX=0):EBX[bit 2]	X86_FEATURE_CAT_L2
    
    L3 cache may support independent control of allocation for
    code and data (CDP = Code/Data Prioritization):
      CPUID.(EAX=10H, ECX=1):ECX[bit 2]	X86_FEATURE_CDP_L3
    
    [ tglx: Fixed up Borislavs comments and moved the feature bits into a gap ]
    Signed-off-by: default avatarFenghua Yu <fenghua.yu@intel.com>
    Acked-by: default avatar"Borislav Petkov" <bp@suse.de>
    Cc: "Ravi V Shankar" <ravi.v.shankar@intel.com>
    Cc: "Tony Luck" <tony.luck@intel.com>
    Cc: "David Carrillo-Cisneros" <davidcc@google.com>
    Cc: "Sai Prakhya" <sai.praneeth.prakhya@intel.com>
    Cc: "Peter Zijlstra" <peterz@infradead.org>
    Cc: "Stephane Eranian" <eranian@google.com>
    Cc: "Dave Hansen" <dave.hansen@intel.com>
    Cc: "Shaohua Li" <shli@fb.com>
    Cc: "Nilay Vaish" <nilayvaish@gmail.com>
    Cc: "Vikas Shivappa" <vikas.shivappa@linux.intel.com>
    Cc: "Ingo Molnar" <mingo@elte.hu>
    Cc: "H. Peter Anvin" <h.peter.anvin@intel.com>
    Link: http://lkml.kernel.org/r/1477142405-32078-5-git-send-email-fenghua.yu@intel.comSigned-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
    4ab15864
scattered.c 1.49 KB