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Joshua Yeong authored
Add clocksource detach/shutdown callback to disable RISC-V timer interrupt when switching out riscv timer as clock source Signed-off-by:
Joshua Yeong <joshua.yeong@starfivetech.com> Reviewed-by:
Anup Patel <anup@brainfault.org> Signed-off-by:
Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20231116105312.4800-1-joshua.yeong@starfivetech.com
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