• Stephane Eranian's avatar
    perf/x86: Fix offcore_rsp valid mask for SNB/IVB · 4fcd6db7
    Stephane Eranian authored
    commit f1923820 upstream.
    
    The valid mask for both offcore_response_0 and
    offcore_response_1 was wrong for SNB/SNB-EP,
    IVB/IVB-EP. It was possible to write to
    reserved bit and cause a GP fault crashing
    the kernel.
    
    This patch fixes the problem by correctly marking the
    reserved bits in the valid mask for all the processors
    mentioned above.
    
    A distinction between desktop and server parts is introduced
    because bits 24-30 are only available on the server parts.
    
    This version of the  patch is just a rebase to perf/urgent tree
    and should apply to older kernels as well.
    Signed-off-by: default avatarStephane Eranian <eranian@google.com>
    Cc: peterz@infradead.org
    Cc: jolsa@redhat.com
    Cc: gregkh@linuxfoundation.org
    Cc: security@kernel.org
    Cc: ak@linux.intel.com
    Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
    [bwh: Backported to 3.2: adjust context; drop the IVB case]
    Signed-off-by: default avatarBen Hutchings <ben@decadent.org.uk>
    4fcd6db7
perf_event_intel.c 46.6 KB