• Stefan Agner's avatar
    drm: mxsfb: fix pixel clock polarity · 53990e41
    Stefan Agner authored
    The DRM subsystem specifies the pixel clock polarity from a
    controllers perspective: DRM_BUS_FLAG_PIXDATA_NEGEDGE means
    the controller drives the data on pixel clocks falling edge.
    That is the controllers DOTCLK_POL=0 (Default is data launched
    at negative edge).
    
    Also change the data enable logic to be high active by default
    and only change if explicitly requested via bus_flags. With
    that defaults are:
    - Data enable: high active
    - Pixel clock polarity: controller drives data on negative edge
    Signed-off-by: default avatarStefan Agner <stefan@agner.ch>
    Acked-by: default avatarMarek Vasut <marex@denx.de>
    Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
    53990e41
mxsfb_crtc.c 8.15 KB