• Eric Biggers's avatar
    crypto: x86/aes-xts - optimize size of instructions operating on lengths · 543ea178
    Eric Biggers authored
    x86_64 has the "interesting" property that the instruction size is
    generally a bit shorter for instructions that operate on the 32-bit (or
    less) part of registers, or registers that are in the original set of 8.
    
    This patch adjusts the AES-XTS code to take advantage of that property
    by changing the LEN parameter from size_t to unsigned int (which is all
    that's needed and is what the non-AVX implementation uses) and using the
    %eax register for KEYLEN.
    
    This decreases the size of aes-xts-avx-x86_64.o by 1.2%.
    
    Note that changing the kmovq to kmovd was going to be needed anyway to
    make the AVX10/256 code really work on CPUs that don't support 512-bit
    vectors (since the AVX10 spec says that 64-bit opmask instructions will
    only be supported on processors that support 512-bit vectors).
    Signed-off-by: default avatarEric Biggers <ebiggers@google.com>
    Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
    543ea178
aesni-intel_glue.c 43.4 KB