• David S. Miller's avatar
    sparc: Detect and handle UltraSPARC-T3 cpu types. · 4ba991d3
    David S. Miller authored
    The cpu compatible string we look for is "SPARC-T3".
    
    As far as memset/memcpy optimizations go, we treat this chip the same
    as Niagara-T2/T2+.  Use cache initializing stores for memset, and use
    perfetch, FPU block loads, cache initializing stores, and block stores
    for copies.
    
    We use the Niagara-T2 perf support, since T3 is a close relative in
    this regard.  Later we'll add support for the new events T3 can
    report, plus enable T3's new "sample" mode.
    
    For now I haven't added any new ELF hwcap flags.  We probably need
    to add a couple, for example:
    
    T2 and T3 both support the population count instruction in hardware.
    
    T3 supports VIS3 instructions, including support (finally) for
    partitioned shift.  One can also now move directly between float
    and integer registers.
    
    T3 supports instructions meant to help with Galois Field and other HPC
    calculations, such as XOR multiply.  Also there are "OP and negate"
    instructions, for example "fnmul" which is multiply-and-negate.
    
    T3 recognizes the transactional memory opcodes, however since
    transactional memory isn't supported: 1) 'commit' behaves as a NOP and
    2) 'chkpt' always branches 3) 'rdcps' returns all zeros and 4) 'wrcps'
    behaves as a NOP.
    
    So we'll need about 3 new elf capability flags in the end to represent
    all of these things.
    Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
    4ba991d3
perf_event.c 35.5 KB