• Masahiro Yamada's avatar
    ARM: uniphier: rework SMP operations to use trampoline code · b1e4006a
    Masahiro Yamada authored
    The complexity of the boot sequence of UniPhier SoC family is
    a PITA due to the following hardware limitations:
    
    [1] No dedicated on-chip SRAM
    SoCs in general have small SRAM, on which a tiny firmware or a boot
    loader can run before SDRAM is initialized.  As UniPhier SoCs do not
    have any dedicated SRAM accessible from CPUs, the locked outer cache
    is used instead.  Due to the ARM specification, to have access to
    the outer cache, the MMU must be enabled.  This is done for all CPU
    cores by the program hard-wired in the boot ROM.  The boot ROM code
    loads a small amount of program (this is usually SPL of U-Boot) from
    a non-volatile device onto the locked outer cache, and the primary
    CPU jumps to it.  The secondary CPUs stay in the boot ROM until they
    are kicked by the primary CPU.
    
    [2] CPUs can not directly jump to SDRAM address space
    As mentioned above, the MMU is enable for all the CPUs with the page
    table hard-wired in the boot ROM.  Unfortunately,...
    b1e4006a
Makefile 63 Bytes