• Huacai Chen's avatar
    MIPS: Check TLB before handle_ri_rdhwr() for Loongson-3 · 5a341331
    Huacai Chen authored
    Loongson-3's micro TLB (ITLB) is not strictly a subset of JTLB. That
    means: when a JTLB entry is replaced by hardware, there may be an old
    valid entry exists in ITLB. So, a TLB miss exception may occur while
    handle_ri_rdhwr() is running because it try to access EPC's content.
    However, handle_ri_rdhwr() doesn't clear EXL, which makes a TLB Refill
    exception be treated as a TLB Invalid exception and tlbp may fail. In
    this case, if FTLB (which is usually set-associative instead of set-
    associative) is enabled, a tlbp failure will cause an invalid tlbwi,
    which will hang the whole system.
    
    This patch rename handle_ri_rdhwr_vivt to handle_ri_rdhwr_tlbp and use
    it for Loongson-3. It try to solve the same problem described as below,
    but more straightforwards.
    
    https://patchwork.linux-mips.org/patch/12591/
    
    I think Loongson-2 has the same problem, but it has no FTLB, so we just
    keep it as is.
    Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
    Cc: Rui Wang <wangr@lemote.com>
    Cc: John Crispin <john@phrozen.org>
    Cc: Steven J . Hill <Steven.Hill@caviumnetworks.com>
    Cc: Fuxin Zhang <zhangfx@lemote.com>
    Cc: Zhangjin Wu <wuzhangjin@gmail.com>
    Cc: Huacai Chen <chenhc@lemote.com>
    Cc: linux-mips@linux-mips.org
    Cc: stable@vger.kernel.org
    Patchwork: https://patchwork.linux-mips.org/patch/15753/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
    5a341331
genex.S 12.8 KB