• Aniruddha Banerjee's avatar
    irqchip/gic: Take lock when updating irq type · aa08192a
    Aniruddha Banerjee authored
    Most MMIO GIC register accesses use a 1-hot bit scheme that
    avoids requiring any form of locking. This isn't true for the
    GICD_ICFGRn registers, which require a RMW sequence.
    
    Unfortunately, we seem to be missing a lock for these particular
    accesses, which could result in a race condition if changing the
    trigger type on any two interrupts within the same set of 16
    interrupts (and thus controlled by the same CFGR register).
    
    Introduce a private lock in the GIC common comde for this
    particular case, making it cover both GIC implementations
    in one go.
    
    Cc: stable@vger.kernel.org
    Signed-off-by: default avatarAniruddha Banerjee <aniruddhab@nvidia.com>
    [maz: updated changelog]
    Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
    aa08192a
irq-gic-common.c 4.22 KB