• Harry Pan's avatar
    perf/x86/intel: Enable C-state residency events for Apollo Lake · 5c10b048
    Harry Pan authored
    Goldmont microarchitecture supports C1/C3/C6, PC2/PC3/PC6/PC10 state
    residency counters, the patch enables them for Apollo Lake platform.
    
    The MSR information is based on Intel Software Developers' Manual,
    Vol. 4, Order No. 335592, Table 2-6 and 2-12.
    Signed-off-by: default avatarHarry Pan <harry.pan@intel.com>
    Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
    Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
    Cc: Jiri Olsa <jolsa@redhat.com>
    Cc: Linus Torvalds <torvalds@linux-foundation.org>
    Cc: Peter Zijlstra <peterz@infradead.org>
    Cc: Stephane Eranian <eranian@google.com>
    Cc: Thomas Gleixner <tglx@linutronix.de>
    Cc: Vince Weaver <vincent.weaver@maine.edu>
    Cc: bp@suse.de
    Cc: davidcc@google.com
    Cc: gs0622@gmail.com
    Cc: lukasz.odzioba@intel.com
    Cc: piotr.luc@intel.com
    Cc: srinivas.pandruvada@linux.intel.com
    Link: http://lkml.kernel.org/r/20170717103749.24337-1-harry.pan@intel.comSigned-off-by: default avatarIngo Molnar <mingo@kernel.org>
    5c10b048
cstate.c 19.7 KB