• Paul Walmsley's avatar
    ARM: OMAP2+: hwmod code/clockdomain data: fix 32K sync timer · 006c7f18
    Paul Walmsley authored
    Kevin discovered that commit c8d82ff6
    ("ARM: OMAP2/3: hwmod data: Add 32k-sync timer data to hwmod
    database") broke CORE idle on OMAP3.  This prevents device low power
    states.
    
    The root cause is that the 32K sync timer IP block does not support
    smart-idle mode[1], and so the hwmod code keeps the IP block in
    no-idle mode while it is active.  This in turn prevents the WKUP
    clockdomain from transitioning to idle.  There is a hardcoded sleep
    dependency that prevents the CORE_L3 and CORE_CM clockdomains from
    transitioning to idle when the WKUP clockdomain is active[2], so the
    chip cannot enter any device low power states.
    
    It turns out that there is no need to take the 32k sync timer out of
    idle.  The IP block itself probably does not have any native idle
    handling at all, due to its simplicity.  Furthermore, the PRCM will
    never request target idle for this IP block while the kernel is
    running, due to the sleep dependency that prevents the WKUP
    clockdomain from idling while the CORE_L3 clockdomain is active.  So
    we can safely leave the 32k sync timer in target-force-idle mode, even
    while we continue to access it.
    
    This workaround is implemented by defining a new clockdomain flag,
    CLKDM_ACTIVE_WITH_MPU, that indicates that the clockdomain is
    guaranteed to be active whenever the MPU is inactive.  If an IP
    block's main functional clock exists inside this clockdomain, and the
    IP block does not support smart-idle modes, then the hwmod code will
    place the IP block into target force-idle mode even when enabled.  The
    WKUP clockdomains on OMAP3/4 are marked with this flag.  (On OMAP2xxx,
    no OCP header existed on the 32k sync timer.)   Other clockdomains also
    should be marked with this flag, but those changes are deferred until
    a later merge window, to create a minimal fix.
    
    Another theoretically clean fix for this problem would be to implement
    PM runtime-based control for 32k sync timer accesses.  These PM
    runtime calls would need to located in a custom clocksource, since the
    32k sync timer is currently used as an MMIO clocksource.  But in
    practice, there would be little benefit to doing so; and there would
    be some cost, due to the addition of unnecessary lines of code and the
    additional CPU overhead of the PM runtime and hwmod code - unnecessary
    in this case.
    
    Another possible fix would have been to modify the pm34xx.c code to
    force the IP block idle before entering WFI.  But this would not have
    been an acceptable approach: we are trying to remove this type of
    centralized IP block idle control from the PM code.
    
    This patch is a collaboration between Kevin Hilman <khilman@ti.com>
    and Paul Walmsley <paul@pwsan.com>.
    
    Thanks to Vaibhav Hiremath <hvaibhav@ti.com> for providing comments on
    an earlier version of this patch.  Thanks to Tero Kristo
    <t-kristo@ti.com> for identifying a bug in an earlier version of this
    patch.  Thanks to Benoît Cousson <b-cousson@ti.com> for identifying
    some bugs in several versions of this patch and for implementation
    comments.
    
    References:
    
    1. Table 16-96 "REG_32KSYNCNT_SYSCONFIG" of the OMAP34xx TRM Rev. ZU
       (SWPU223U), available from:
       http://www.ti.com/pdfs/wtbu/OMAP34x_ES3.1.x_PUBLIC_TRM_vzU.zip
    
    2. Table 4-72 "Sleep Dependencies" of the OMAP34xx TRM Rev. ZU
       (SWPU223U)
    
    3. ibid.
    
    Cc: Tony Lindgren <tony@atomide.com>
    Cc: Vaibhav Hiremath <hvaibhav@ti.com>
    Cc: Benoît Cousson <b-cousson@ti.com>
    Cc: Tero Kristo <t-kristo@ti.com>
    Tested-by: default avatarKevin Hilman <khilman@ti.com>
    Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
    Signed-off-by: default avatarKevin Hilman <khilman@ti.com>
    006c7f18
clockdomains2xxx_3xxx_data.c 2.62 KB