• Marcin Ziemianowicz's avatar
    clk: at91: PLL recalc_rate() now using cached MUL and DIV values · a982e45d
    Marcin Ziemianowicz authored
    When a USB device is connected to the USB host port on the SAM9N12 then
    you get "-62" error which seems to indicate USB replies from the device
    are timing out. Based on a logic sniffer, I saw the USB bus was running
    at half speed.
    
    The PLL code uses cached MUL and DIV values which get set in set_rate()
    and applied in prepare(), but the recalc_rate() function instead
    queries the hardware instead of using these cached values. Therefore,
    if recalc_rate() is called between a set_rate() and prepare(), the
    wrong frequency is calculated and later the USB clock divider for the
    SAM9N12 SOC will be configured for an incorrect clock.
    
    In my case, the PLL hardware was set to 96 Mhz before the OHCI
    driver loads, and therefore the usb clock divider was being set
    to /2 even though the OHCI driver set the PLL to 48 Mhz.
    
    As an alternative explanation, I noticed this was fixed in the past by
    87e2ed33 ("clk: at91: fix recalc_rate implementation of PLL
    driver") but the bug was later re-introduced by 1bdf0232 ("clk:
    at91: make use of syscon/regmap internally").
    
    Fixes: 1bdf0232 ("clk: at91: make use of syscon/regmap internally)
    Cc: <stable@vger.kernel.org>
    Signed-off-by: default avatarMarcin Ziemianowicz <marcin@ziemianowicz.com>
    Acked-by: default avatarBoris Brezillon <boris.brezillon@bootlin.com>
    Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
    a982e45d
clk-pll.c 12.4 KB