• Russell King's avatar
    ALSA: AACI: allow writes to MAINCR to take effect · 7c289385
    Russell King authored
    The AACI TRM requires the MAINCR enable bit to be held zero for two
    bitclk cycles plus three apb_pclk cycles.  Use a delay of 1us to
    ensure this.
    
    Ensure that writes to MAINCR to change the addressed codec only happen
    when required, and that they take effect in a similar manner to the
    above, otherwise we seem to occasionally have stuck slot busy bits.
    Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
    7c289385
aaci.c 25.6 KB