• Razmik Karapetyan's avatar
    usb: dwc2: Add ACG support to the driver · 66e77a24
    Razmik Karapetyan authored
    Added function for supporting Active Clock Gating functionality
    in the driver.
    
    PCGCCTL1 (Power and Clock Control) register will be used
    for controlling the core`s active clock gating feature, and
    the previously reserved 12th bit in GHWCFG4 now indicates that the
    controller supports the Dynamic Power Reduction (Active Clock Gating)
    during no traffic scenarios such as L0, idle, resume and suspend
    states.
    
    dwc2_enable_acg() function sets GATEEN bit in PCGCCTL1 register
    and enables ACG, if it supported.
    
    According to ACG functional specification, enabling of ACG feature
    in host mode done in host initialization, before turning Vbus on,
    specifically in dwc2_core_host_init function.
    
    Enabling of ACG feature in device mode done in device initialization,
    before clearing the SftDiscon bit in DCTL.
    This bit was cleared in dwc2_hsotg_core_connect() function.So
    dwc2_enable_acg() called before dwc2_core_connect() calls.
    Signed-off-by: default avatarRazmik Karapetyan <razmik@synopsys.com>
    Signed-off-by: default avatarGrigor Tovmasyan <tovmasya@synopsys.com>
    Signed-off-by: default avatarFelipe Balbi <felipe.balbi@linux.intel.com>
    66e77a24
hcd.c 150 KB