Add documentation for the RZ/G3S CPG.  The RZ/G3S CPG module is almost
identical to the one available in RZ/G2{L,UL}, the exception being some
core clocks as follows:
  - The SD clock is composed of a mux and a divider, and the divider
    has some limitations (div = 1 cannot be set if mux rate is 800MHz),
  - There are 3 SD clocks,
  - The OCTA and TSU clocks are specific to RZ/G3S,
  - PLL1/4/6 are specific to RZ/G3S with its own computation formula.
Even with this RZ/G3S could use the same bindings as RZ/G2L.

Along with documentation bindings for the RZ/G3S (R9A08G045) Clock Pulse
Generator (CPG) core clocks, module clocks and resets were added.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929053915.1530607-13-claudiu.beznea@bp.renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>