• Matthew Brost's avatar
    drm/i915/guc: Add delay to disable scheduling after pin count goes to zero · 6a079903
    Matthew Brost authored
    Add a delay, configurable via debugfs (default 34ms), to disable
    scheduling of a context after the pin count goes to zero. Disable
    scheduling is a costly operation as it requires synchronizing with
    the GuC. So the idea is that a delay allows the user to resubmit
    something before doing this operation. This delay is only done if
    the context isn't closed and less than a given threshold
    (default is 3/4) of the guc_ids are in use.
    
    As temporary WA disable this feature for the selftests. Selftests are
    very timing sensitive and any change in timing can cause failure. A
    follow up patch will fixup the selftests to understand this delay.
    
    Alan Previn: Matt Brost first introduced this series back in Oct 2021.
    However no real world workload with measured performance impact was
    available to prove the intended results. Today, this series is being
    republished in response to a real world workload that benefited greatly
    from it along with measured performance improvement.
    
    Workload description: 36 containers were created on a DG2 device where
    each container was performing a combination of 720p 3d game rendering
    and 30fps video encoding. The workload density was configured in a way
    that guaranteed each container to ALWAYS be able to render and
    encode no less than 30fps with a predefined maximum render + encode
    latency time. That means the totality of all 36 containers and their
    workloads were not saturating the engines to their max (in order to
    maintain just enough headrooom to meet the min fps and max latencies
    of incoming container submissions).
    
    Problem statement: It was observed that the CPU core processing the i915
    soft IRQ work was experiencing severe load. Using tracelogs and an
    instrumentation patch to count specific i915 IRQ events, it was confirmed
    that the majority of the CPU cycles were caused by the
    gen11_other_irq_handler() -> guc_irq_handler() code path. The vast
    majority of the cycles was determined to be processing a specific G2H
    IRQ: i.e. INTEL_GUC_ACTION_SCHED_CONTEXT_MODE_DONE. These IRQs are sent
    by GuC in response to i915 KMD sending H2G requests:
    INTEL_GUC_ACTION_SCHED_CONTEXT_MODE_SET. Those H2G requests are sent
    whenever a context goes idle so that we can unpin the context from GuC.
    The high CPU utilization % symptom was limiting density scaling.
    
    Root Cause Analysis: Because the incoming execution buffers were spread
    across 36 different containers (each with multiple contexts) but the
    system in totality was NOT saturated to the max, it was assumed that each
    context was constantly idling between submissions. This was causing
    a thrashing of unpinning contexts from GuC at one moment, followed quickly
    by repinning them due to incoming workload the very next moment. These
    event-pairs were being triggered across multiple contexts per container,
    across all containers at the rate of > 30 times per sec per context.
    
    Metrics: When running this workload without this patch, we measured an
    average of ~69K INTEL_GUC_ACTION_SCHED_CONTEXT_MODE_DONE events every 10
    seconds or ~10 million times over ~25+ mins. With this patch, the count
    reduced to ~480 every 10 seconds or about ~28K over ~10 mins. The
    improvement observed is ~99% for the average counts per 10 seconds.
    Signed-off-by: default avatarMatthew Brost <matthew.brost@intel.com>
    Signed-off-by: default avatarAlan Previn <alan.previn.teres.alexis@intel.com>
    Reviewed-by: default avatarJohn Harrison <John.C.Harrison@Intel.com>
    Signed-off-by: default avatarJohn Harrison <John.C.Harrison@Intel.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20220817020511.2180747-3-alan.previn.teres.alexis@intel.com
    6a079903
intel_guc_debugfs.c 3.71 KB