• Lars-Peter Clausen's avatar
    ASoC: adau17x1: Add support for specifying the MCLK using the CCF · 5d76de61
    Lars-Peter Clausen authored
    The devices from the ADAU17X1 family all have a MCLK clock input which
    supplies the master clock for the device. The master clock is used as the
    input clock for the PLL. Currently the MCLK rate as well as the desired PLL
    output frequency need to be supplied by calling snd_soc_dai_set_pll() form
    a machine driver.
    
    Add support for specifying the MCLK using the common clock framework. In
    addition to that also automatically configure the PLL to a suitable rate
    if the master clock was provided using the CCW. This allows to use the
    CODEC driver without any special configuration requirements from the
    machine driver.
    
    While the PLL output frequency can be configured over a (more or less)
    continuous range the narrowness of the range and the other constraints of
    the clocking tree usually only result in two output frequencies that will
    actually be chosen. One for 44.1kHz based rates and one for 48kHz based
    rates, these are the rates that the automatic PLL configuration will use.
    For the rare case where a non-standard setup is required a machine driver
    can disable the auto-configuration and configure a custom frequency using
    the existing mechanisms.
    
    If the common clock framework is not enabled clk_get() will return NULL and
    the driver will function as before and the clock rate needs to be
    configured manually.
    Signed-off-by: default avatarLars-Peter Clausen <lars@metafoo.de>
    Signed-off-by: default avatarMark Brown <broonie@kernel.org>
    5d76de61
adau17x1.c 24.2 KB