• Kamal Dasu's avatar
    spi: bcm-qspi: Drive MSPI peripheral SSb pin on cs_change · 742d5958
    Kamal Dasu authored
    As per the spi core implementation for MSPI devices when the transfer is
    the last one in the message, the chip may stay selected until the next
    transfer. On multi-device SPI busses with nothing blocking messages going
    to other devices, this is just a performance hint; starting a message to
    another device deselects this one. But in other cases, this can be used
    to ensure correctness. Some devices need protocol transactions to be built
    from a series of spi_message submissions, where the content of one message
    is determined by the results of previous messages and where the whole
    transaction ends when the chipselect goes intactive.
    
    On CS change after completing the last serial transfer, the MSPI driver
    drives SSb pin CDRAM register correctly according comments in core spi.h
    as shown below:
    
    case 1) EOM =1, cs_change =0: SSb inactive
    case 2) EOM =1, cs_change =1: SSb active
    case 3) EOM =0, cs_change =0: SSb active
    case 4) EOM =0, cs_change =1: SSb inactive
    Signed-off-by: default avatarKamal Dasu <kdasu.kdev@gmail.com>
    Link: https://lore.kernel.org/r/20200420190853.45614-5-kdasu.kdev@gmail.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
    742d5958
spi-bcm-qspi.c 36.1 KB