• Claudiu Beznea's avatar
    clk: renesas: rzg2l: Extend power domain support · 0c8a59b3
    Claudiu Beznea authored
    RZ/{G2L, V2L, G3S}-based CPG versions have support for saving extra
    power when clocks are disabled by activating module standby.  This is
    done through MSTOP-specific registers that are part of CPG.  Each
    individual module has one or more bits associated with one MSTOP
    register (see table "Registers for Module Standby Mode" from HW
    manuals).  Hardware manual associates modules' clocks with one or more
    MSTOP bits.  There are 3 mappings available (identified by researching
    RZ/G2L, RZ/G3S, RZ/V2L HW manuals):
    
    case 1: N clocks mapped to N MSTOP bits (with N={0, ..., X})
    case 2: N clocks mapped to 1 MSTOP bit  (with N={0, ..., X})
    case 3: N clocks mapped to M MSTOP bits (with N={0, ..., X}, M={0, ..., Y})
    
    Case 3 has been currently identified on RZ/V2L for the VCPL4 module.
    
    To cover all three cases, the individual platform drivers will provide
    the clock driver with MSTOP register offsets and associated bits in this
    register as a bitmask, and the clock driver will apply this bitmask to
    the proper MSTOP register.
    
    The MSTOP support was implemented through power domains.
    Platform-specific clock drivers will register an array of type struct
    rzg2l_cpg_pm_domain_init_data, which will be used to instantiate
    properly the power domains.
    Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
    Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
    Reviewed-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
    Link: https://lore.kernel.org/r/20240422105355.1622177-7-claudiu.beznea.uj@bp.renesas.comSigned-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
    0c8a59b3
rzg2l-cpg.c 48.5 KB