• James Hogan's avatar
    KVM: MIPS/T&E: Implement CP0_EBase register · 7801bbe1
    James Hogan authored
    The CP0_EBase register is a standard feature of MIPS32r2, so we should
    always have been implementing it properly. However the register value
    was ignored and wasn't exposed to userland.
    
    Fix the emulation of exceptions and interrupts to use the value stored
    in guest CP0_EBase, and fix the masks so that the top 3 bits (rather
    than the standard 2) are fixed, so that it is always in the guest KSeg0
    segment.
    
    Also add CP0_EBASE to the KVM one_reg interface so it can be accessed by
    userland, also allowing the CPU number field to be written (which isn't
    permitted by the guest).
    Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
    Cc: Paolo Bonzini <pbonzini@redhat.com>
    Cc: "Radim Krčmář" <rkrcmar@redhat.com>
    Cc: Ralf Baechle <ralf@linux-mips.org>
    Cc: linux-mips@linux-mips.org
    Cc: kvm@vger.kernel.org
    7801bbe1
api.txt 127 KB