• Marek Vasut's avatar
    ARM: dts: socfpga: fine-tune L2 cache configuration · 7c38dc62
    Marek Vasut authored
    Enable double-linefill and increase prefetch offset, which gives
    considerable read performance boost. The following numbers were
    obtained using lmbench 3.0 bw_mem tool, for easier comparison, the
    numbers are pasted in two columns. The test machine has Cyclone V
    SoC running at 800MHz MPU clock and 512MiB 333MHz 16bit DDR3 DRAM.
    
    Without patch   | With patch
    $ for i in rd wr rdwr cp fwr frd fcp bzero bcopy ; do echo $i ; bw_mem 64M $i ; done
    rd              | rd
    64.00 526.46    | 64.00 1151.06
    wr              | wr
    64.00 329.95    | 64.00 346.14
    rdwr            | rdwr
    64.00 342.07    | 64.00 367.24
    cp              | cp
    64.00 239.79    | 64.00 322.47
    fwr             | fwr
    64.00 1027.90   | 64.00 1025.38
    frd             | frd
    64.00 322.36    | 64.00 641.89
    fcp             | fcp
    64.00 256.99    | 64.00 408.41
    bzero           | bzero
    64.00 1028.43   | 64.00 1025.07
    bcopy           | bcopy
    64.00 294.73    | 64.00 357.19
    Signed-off-by: default avatarMarek Vasut <marex@denx.de>
    Signed-off-by: default avatarDinh Nguyen <dinguyen@opensource.altera.com>
    7c38dc62
socfpga.dtsi 21 KB