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Herve Codina authored
Add support for the time slot assigner (TSA) available in some PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321. The QE TSA is similar to the CPM1 TSA except that it uses UCCs (Unified Communication Controllers) instead of SCCs (Serial Communication Controllers). Also, compared against the CPM1 TSA, this QE TSA can handle up to 4 TDMs instead of 2 and allows to configure the logic level of sync signals. At a lower level, compared against CPM TSA implementation, some registers are slightly different even if same features are present. Signed-off-by:
Herve Codina <herve.codina@bootlin.com> Reviewed-by:
Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-15-herve.codina@bootlin.com Signed-off-by:
7ac94702
