drivers/clk/at91/clk-sam9x60-pll.c · 7ddb58cb0ecae8e8b6181d736a87667cc9ab8389 · Kirill Smelkov / linux

clk: at91: clk-sam9x60-pll: add notifier for div part of PLL · 1e229c21

Claudiu Beznea authored Oct 11, 2021

SAM9X60's PLL which is also part of SAMA7G5 is composed of 2 parts:
one fractional part and one divider. On SAMA7G5 the CPU PLL could be
changed at run-time to implement DVFS. The hardware clock tree on
SAMA7G5 for CPU PLL is as follows:

                       +---- div1 ----------------> cpuck
                       |
FRAC PLL ---> DIV PLL -+-> prescaler ---> div0 ---> mck0

The div1 block is not implemented in Linux; on prescaler block it has
been discovered a bug on some scenarios and will be removed from Linux
in next commits. Thus, the final clock tree that will be used in Linux
will be as follows:

                       +-----------> cpuck
                       |
FRAC PLL ---> DIV PLL -+-> div0 ---> mck0

It has been proposed in [1] to not introduce a new CPUFreq driver but
to overload the proper clock drivers with proper operation such that
cpufreq-dt to be used. To accomplish this DIV PLL and div0 implement
clock notifiers which appli...

1e229c21

clk-sam9x60-pll.c 20.3 KB

Replace clk-sam9x60-pll.c