• Will Deacon's avatar
    ARM: 7658/1: mm: fix race updating mm->context.id on ASID rollover · 810f6379
    Will Deacon authored
    commit 37f47e3d upstream.
    
    If a thread triggers an ASID rollover, other threads of the same process
    must be made to wait until the mm->context.id for the shared mm_struct
    has been updated to new generation and associated book-keeping (e.g.
    TLB invalidation) has ben performed.
    
    However, there is a *tiny* window where both mm->context.id and the
    relevant active_asids entry are updated to the new generation, but the
    TLB flush has not been performed, which could allow another thread to
    return to userspace with a dirty TLB, potentially leading to data
    corruption. In reality this will never occur because one CPU would need
    to perform a context-switch in the time it takes another to do a couple
    of atomic test/set operations but we should plug the race anyway.
    
    This patch moves the active_asids update until after the potential TLB
    flush on context-switch.
    Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
    Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
    Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
    Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
    810f6379
context.c 5.57 KB