• lipeng's avatar
    net: hns: Avoid Hip06 chip TX packet line bug · 820c90cb
    lipeng authored
    There is a bug on Hip06 that tx ring interrupts packets count will be
    clear when drivers send data to tx ring, so that the tx packets count
    will never upgrade to packets line, and cause the interrupts engendered
    was delayed.
    Sometimes, it will cause sending performance lower than expected.
    
    To fix this bug, we set tx ring interrupts packets line to 1 forever,
    to avoid count clear. And set the gap time to 20us, to solve the problem
    that too many interrupts engendered when packets line is 1.
    
    This patch could advance the send performance on ARM  from 6.6G to 9.37G
    when an iperf send thread on ARM and an iperf send thread on X86 for XGE.
    Signed-off-by: default avatarlipeng <lipeng321@huawei.com>
    Signed-off-by: default avatarSalil Mehta <salil.mehta@huawei.com>
    Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
    820c90cb
hns_dsaf_rcb.c 32.1 KB